VHDL Ref

squishLogic

The pocket translator for hardware description languages. VHDL Ref is a quick reference for VHDL, Verilog, and SystemVerilog, written by engineers for engineers. For every construct in VHDL it shows the equivalent in Verilog, and vice versa. Whether you are an FPGA or ASIC designer who thinks in one language but has to read the other, a verification engineer working in SystemVerilog, or an engineering student in your first digital design course, VHDL Ref puts the answer one tap away. + 328 entries covering every keyword, operator, and data type in both languages + Cross-language equivalents on every entry: see how the other language says it + A simple worked example for every single entry + SystemVerilog coverage, plus VHDL 2008 and Verilog 2001 notation + All pre-defined VHDL attributes + All Verilog primitive gates and drive strengths + Filter by language and by element type + Works completely offline: in the lab, on a plane, behind the firewall + No ads, no subscription, no account, no tracking Native on iPhone, iPad, and Mac (a real Mac app, not a port), so the same reference sits next to your simulator at your desk and rides in your pocket everywhere else. Note: VHDL Ref is a reference, not a simulator or compiler. It is the book you keep open beside your tools, rebuilt for the device you always have with you.